This relates to solid-state image sensors and, more specifically, to image sensors with small size pixels that are either front-side illuminated or back-side-illuminated. The small pixel size helps to reduce the cost of image sensor arrays. Sensor performance, however, should not be compromised as the size of pixels is reduced. Conventional image sensors detect light by converting impinging photons into electrons that are integrated (collected) in sensor pixels. Upon completion of each integration cycle, the collected charge is converted into voltage signals, which are then supplied to corresponding output terminals associated with the image sensor. Typically, the charge to voltage conversion is performed directly within the pixels, and the resulting analog pixel voltage signals are transferred to the output terminals through various pixel addressing and scanning schemes. The analog signal can sometimes be converted on-chip to a digital equivalent before being conveyed off-chip. Each pixel includes a buffer amplifier commonly referred to as a source follower (SF), which is used to drive output sensing lines that are connected to the pixels via respective address transistors.
After the charge-to-voltage conversion is complete and after the resulting signals are transferred out from the pixels, the pixels are reset before a subsequent integration cycle begins. In pixels having floating diffusions (FD) serving as the charge detection node, this reset operation is accomplished by momentarily turning on a reset transistor that connects the FD node to a fixed voltage reference for draining (or removing) any charge remaining at the FD node.
Removing charge from the floating diffusion node using the reset transistor, however, generates kTC-reset noise as is well known in the art. The kTC noise must be removed using correlated double sampling (CDS) signal processing technique in order to achieve desired low noise performance. Image sensors that utilize CDS typically require three transistors (3T) or four transistors (4T) per pixel. An example of the 4T pixel circuit with a pinned photo-diode can be found in Lee (U.S. Pat. No. 5,625,210), incorporated herein as a reference.
FIG. 1 is a simplified rendering of a cross-sectional side view of a conventional image sensor pixel 100. As shown in FIG. 1, conventional image sensor pixel 100 includes a photodiode 107 configured to collect photon-generated carriers, charge transfer transistor gate 108, N+ doped floating diffusion region 111, reset transistor gate 109, and source follower transistor gate 110. The reset transistor and the source follower transistor share an N+ drain region 112 that is biased to a fixed positive power supply voltage Vdd. The source follower transistor has an N+ source region 113 that is connected to a column sensing line Vout through metal via 115 (i.e., an output line to which each pixel in a given column is connected).
Note that floating diffusion region 111 is connected to source follower gate 110 via connection 116. This connection supplies the signal collected at the floating diffusion region to the source follower transistor gate. Pixel 100 may include an address transistor interposed between the region 113 and sensing line Vout that is common to all pixels in a given column of image sensor pixels. For simplicity, the address transistor is not shown in FIG. 1.
Pixel 100 is fabricated in an epitaxial substrate 101. A P+ doped layer 102 is deposited on the back surface of the sensor if the sensor is a back-side-illuminated image sensor. Substrate 101 may also be deposited on a substantially thicker P+ substrate (relative to layer 102) for the front-side-illuminated image sensors. Epitaxial layer 101 is covered by an oxide layer 103 that provides electrical isolation for gates 108, 109, and 110. Oxide material 103 typically extends into and fills up shallow trench isolation (STI) regions 114. An additional oxide layer 104 is deposited over the gates and serves as isolation for the metal wiring formed over pixel 100. Additional oxide isolation layers and the metal wiring layers are typically deposited over the top of pixel 100 (not shown).
Photodiode 107 includes a P+ layer 105 that is formed directly below layer 103 and that is connected to ground. This P+ doping layer reduces dark current by filling the silicon-silicon dioxide interface states with holes. Photon generated electrons are accumulated in N-type doped region 106. The accumulated charge is transferred to N+ floating diffusion region 111 when transfer gate 108 is turned on. Prior to turning on charge transfer gate 108, floating diffusion region 111 needs to be reset by pulsing signal that is supplied to gate 109 of the reset transistor.
An additional bottom P-implant (BTP) layer 117 is extended from P+ layer 105 formed under STI region 114 to the region under reset transistor gate 109 and source follower transistor gate 110 (see, FIG. 1). Layer 117 is connected to ground and serves to block photon generated electrons from entering regions 111, 112, and 113.
As is apparent from FIG. 1, a large portion of the valuable pixel area is occupied by transistor gates 108, 109, and 110. Forming transistors side-by-side on the surface of substrate 101 using this arrangement may be disadvantageous. It may therefore be desirable to provide image sensors with reduced pixel area, where a smaller portion of the pixel area is occupied by transistors and a larger portion of the pixel area is occupied by the photodiode.